Diffused metal oxide semiconductor (DMOS) devices are characterized by a source region and a backgate region that are diffused at the same time. The transistor channel is formed by the difference in the two diffusions and not a separation implantation, which results in a decreased channel length. The shorter channel allows for low power dissipation and high speed capability.
A lateral diffused metal oxide semiconductor (LDMOS) device has its source and drain at the surface of the wafer causing a lateral current. Two important parameters in the design of LDMOS devices are breakdown voltage and on-state resistance. It is preferred to have a high breakdown voltage and a low on-state resistance to provide a device having relatively lower power consumption when operated under high voltage. Additionally, a low on-state resistance provides a higher drain current when the device is saturated, which tends to improve the operating speed of the device.
FIG. 1 illustrates a plan view of a drift region of a conventional LDMOS device. The LDMOS device 1 of FIG. 1 having a LDMOS region 10 called out by the box as illustrated. The LDMOS device 1 is defined by a source side 20 and a drain side 30.
FIG. 2 illustrates a plan view of the LDMOS region 10 called out in FIG. 1. The LDMOS region 10 having a plurality of p-type diffusion layers or p-top regions 40 substantially continuously extending from the source side 20 to the drain side 30, the plurality of p-top regions 40 disposed in a high voltage n-type well (HVNW). Thus, the conventional LDMOS region 10 is defined by sections of n-type grade or n-grade region 50 disposed on the plurality of p-top regions 40 separated by n-grade region 50 not disposed over any p-top layer.
FIG. 3A is a cross-sectional view of FIG. 2 taken along the AA′ section line. This representation of a conventional LDMOS has a p-substrate 60 in which an HVNW 70 has been disposed. A first p-well 80 is formed in the p-substrate 60 while a second p-well 90 is formed in the HVNW 70, the first p-well 80 having a p+ doped region 100 and the second p-well 90 having another p+ doped region 110 adjacent to an n+ doped source region 120. An n+ doped drain region 130 has been formed in the HVNW 70. This section of the LDMOS region 10 is represented by an n-grade region 50 disposed on one of the plurality of p-top regions 40. An etched field oxide isolation region 140 substantially separates the doped regions 100, 110, 120, 130.
Any control gate structure 150 known in the art may be used in the LDMOS device. For example the control gate structure 150 may comprise a conductive layer disposed on a dielectric layer. The control gate structure 150 may additionally comprise dielectric sidewall spacers. An etched interlayer dielectric (ILD) layer 160 is disposed over the defined structure. A first etched metal layer 170 is provided having a network of contacts through the ILD layer 160. The exemplary conventional LDMOS of FIG. 3A additionally shows an inter-metal dielectric (IMD) layer 180 upon which is disposed a second etched metal layer 190 providing a network of contacts through the IMD layer 180.
FIG. 3B is a cross-sectional view of FIG. 2 taken along the BB′ section line. This cross-sectional view of the conventional LDMOS has the same structure identified in FIG. 3A except that a p-top layer is not disposed in the HVNW 70.
High voltage LDMOS devices have a variety of uses in semiconductors. For example, LDMOS devices may be used to convert relatively high voltage to relatively low voltage or as switching power transistors that are configured to drive a load. However, the specific on-resistance of the conventional high voltage LDMOS can still be too high as a result of the interaction between the n-grade region and the fully doped p-type region. There remains a need in the art for improved LDMOS devices, in particular, high voltage LDMOS devices having an even lower specific on-resistance.